A conventional method for manufacturing a reverse blocking IGBT will be described. A first prior art is a method of coating a dopant source and performing thermal diffusion from the surface of the dicing region on a wafer (silicon) in advance, before forming the gate/emitter structure constituting the reverse blocking IGBT, as shown in FIG. 26, where a deep p-isolation layer is formed, the wafer is thinned so that the p-isolation layer is exposed after the gate/emitter structure is formed, and a p-collector layer, to be connected to the p-isolation layer, is formed by performing ion implantation and annealing on the rear face of the thinned wafer (e.g. see Patent Document 1 listed below).
According to a second prior art, shown in FIG. 27, an MOS structure is formed in the IGBT front surface process, the rear face of the wafer is lapped, and the MOS structure side is bonded with a glass substrate. Then the front face and the back face are flipped over, a mask pattern is formed on the rear face which is now positioned on top, and V grooves are formed by anisotropic wet etching using an alkaline solution, for example. A p-diffusion layer is formed on the front face of the wafer near the dicing region, so as to form the gate/emitter structure (MOS structure). Then the mask is removed, and Boron ion implantation and laser annealing are simultaneously performed on the side walls of the V grooves and rear face of the wafer, to form the p-isolation layer and p-collector layer, a metal electrode film (e.g. Au layer) to be the collector electrode, is formed thereon, and the reverse blocking IGBT is formed by pickup (e.g. see Patent Document 2, Patent Document 3 and Non-patent Document 1 listed below). FIG. 28 is a cross-sectional view of a key section of the outer periphery area of the reverse blocking IGBT formed by the second prior art. The p-diffusion layer on the front face side of the wafer and the p-collector layer on the rear face side of the wafer are connected by the p-isolation layer formed on the side walls of the V grooves.
As laser oscillators decrease in size and price and increase in life and performance, laser irradiation processing is becoming more widely used for silicon wafers. One example is the above mentioned laser annealing processing for activating dopants implanted by ion implantation. Another available method for activating dopants implanted by ion implantation is a furnace annealing processing, but in this case, the processing temperature is limited by the heat resistance temperature of the metal electrode film and protective film already formed on the front face of the wafer, therefore processing at high temperature is not possible, and the dopant activation ratio is low. The case of laser annealing processing using a pulse laser can instantaneously and locally heat only the surface layer region on the rear face of the wafer, so thermal damage is not caused to the metal electrode film and protective film already formed on the front face side of the wafer. Therefore the dopants on the rear face side can be activated at a high activation ratio, regardless the heat resistance temperature of the structure on the front face side of the wafer.    Patent Document 1: Japanese Patent Application Laid-Open No. 2004-363328    Patent Document 2: Japanese Patent Application Laid-Open No. 2006-303410    Patent Document 3: Japanese Patent Application Laid-Open No. 2006-278382    Non-patent Document 1: Kazuo Shimoyama, and two others: “New Isolation Technique for High Breakdown Voltage Reverse Blocking IGBT”, “[Electronic Device/Semiconductor Power Conversion], General Power Device and Semiconductor Power Conversion”, Technical Society of the Institute of Electrical Engineers of Japan, EDD-06-52, SPC-06-124
In the case of forming the p-isolation layer from the front face of the semiconductor substrate to the collector layer surface of the rear face thereof only by thermal diffusion according to the first prior art, a very thick thermal oxide film must be formed so that the Boron forming the p-isolation layer does not penetrate through the oxide film masking the active portion. In order to form this thick thermal oxide film, thermal oxidation processing must be performed at high temperature for a long time, which increases the manufacturing cost.
The diffusion of dopants requires a lengthy processing time at high temperature, so throughput dramatically drops, and the dopants are inevitably diffused in the lateral direction since the dopants isotropically diffuse from the mask opening portion to the silicon bulk, which causes problems in reducing device pitch and chip size.
An available method for preventing this is the second prior art, where the thinning processing of the wafer is performed after forming the device structure on the front face, such as the gate/emitter structure, as mentioned above, and after the wafer is bonded with the glass support substrate so as to face the front face of the device, the tapered V grooves are pierced through from the rear face of the wafer to the front face of the wafer by wet etching, and the p-isolation layer is formed on the side wall faces of the grooves by ion implantation and laser annealing. Here “tapered groove” refers to a groove having an inclined side wall at an angle where the groove width spreads from the bottom portion to the opening.
The heat treatment time and device pitch are dramatically decreased by this method, but piercing all the way to the front face of the wafer causes separation and individual chips to fall, so the wafer must be bonded with the glass substrate or the like, which makes processing complicated and increases manufacturing cost. After forming the pierced V grooves (penetrated grooves), ion implantation and laser annealing are performed, but as FIG. 29 shows, adhesive, which bonds the wafer and the glass substrate, is irradiated by the laser beam in portion A, that is a portion where the penetrated grooves (based portion of the V grooves), so a special expensive adhesive, which is not affected by irradiation of the laser beam, must be used, and therefore manufacturing cost increases.
Then the collector electrode is formed by sputtering after laser annealing, but a heat resistant expensive adhesive must be used so as not to be affected even if the adhesive is heated by this sputtering processing, which increases manufacturing cost. Or an expensive sputtering device having a special cooling mechanism must be used so that the heat temperature does not rise.
Another problem is that the sintering processing temperature, after sputtering, is limited by the heat resistance temperature of the adhesive. Furthermore, a special adhesive must be selected and the expensive adhesive must be used so that the volatile constituents from the adhesive do not drop the degree of vacuum of the sputtering device. In other words, the manufacturing cost increases if the conventional method is used.
Now a carrier profile depending on the tilt angle of the side wall of the V groove is checked. FIG. 30 is a graph depicting the carrier profile depending on the tilt angle of the side wall of the groove. In FIG. 30, the ordinate indicates the carrier concentration, and the abscissa indicates the depth. Here the tilt angle of the side wall of the V groove refers to an angle formed by a line on the opening portion of the groove, extending from the plane of the rear face of the wafer, where this opening portion is formed and the side wall of the groove. FIG. 30 shows a profile of the activated carriers on the side wall when laser annealing is performed by irradiating the pulse laser of which wavelength is 527 nm onto the plane where the opening of the V groove is formed from the vertical direction, with a 1.4 J/cm2 irradiation energy density. In this case, it is assumed that dopants have already been implanted by Boron ion implantation. FIG. 30 shows carrier profiles when the tilt angles of the side wall of the V groove are 0° and 55° to 85° (at every 5°), which were cited from the above mentioned Non-patent Document 1.
When V grooves are formed on the rear face of the wafer by anisotropic wet etching using an alkaline solution, V grooves are formed to be the {111} plane since the rear face of the wafer is the {100} plane. Therefore the tilt angle of the side wall of the V groove is relatively small, 54.7°, and tapering is wide. Because of this, the difference between the width of the bottom portion of the groove and the width of the opening portion increases, and the side wall of the groove can absorb more laser beams irradiated vertically onto the rear face side of the wafer. Therefore if laser annealing is performed under the conditions of forming a high concentration p-collector layer on the plane (tilt angle″ 0°) of the rear face of the wafer, as shown in FIG. 30, dopants implanted in the side wall of the V groove can be activated at the same time.
However if the tilt angle of the side wall of the V groove is greater than 60°, the activation ratio of the dopants decreases as the tilt angle increases, as shown in FIG. 30. This is because if the tilt angle of the V groove is θ, the effective irradiation energy density on the side wall of the V groove drops to a value multiplied by cos θ.
A known method for forming the V grooves, other than anisotropic wet etching using an alkaline solution, is an anisotropic dry etching called RIE (Reactive Ion Etching) using HBr, NF3 or He/O2 as the etching gas. If grooves are formed by RIE etching, it is known that the tilt angle of the side wall of the groove becomes 90° or an angle close to this, but a groove of which tilt angle of the side wall is smaller than 90°, that is a tapered groove, can be formed by relatively increasing the flow rate of He/O2, for example. However more black silicon tends to be generated as the flow rate of He/O2 increases. Another problem of RIE etching is that the tilt angle of the side wall of the groove can be decreased only down to about 75°.
Another known method for forming tempered grooves, is, for example, a method of performing half cut dicing using a dicing blade of which edge is tapered.
RIE etching and half cut dicing are appropriate for forming an isolation layer using tapered grooves in the outer periphery portion of the reverse blocking IGBT chip having a trench gate structure, since tapered grooves can be formed regardless the plane orientation and crystal orientation of the wafer.
FIG. 31 and FIG. 32 are diagrams depicting the problems of performing laser annealing on a tapered groove. FIG. 31 and FIG. 32 show a case of performing laser annealing by irradiating laser onto a tapered groove vertical to a plane where an opening portion of the tapered grove is formed. In FIG. 31 and FIG. 32, the tilt angle of the side wall of the groove is assumed to be 75°.
As FIG. 31 shows, if the irradiation energy density of the laser beam 64, that is irradiated onto the plane, is 100%, then the effective irradiation energy density of the laser beam 64, irradiated onto the side wall of the tapered groove, is 100×cos 75°=25.9%, that is, a drop to about ¼ of that in the case of the plane. This means that with the irradiation energy density conforming to the conditions appropriate for the plane, dopants implanted into the side wall of the tapered groove cannot be activated.
In concrete terms, in order to form the p-collector layer on a plane, of which tilt angle is 0°, on the rear face side of the wafer by activating Boron implanted by ion implantation, the laser beam 64, of which irradiation energy density is 1.4 J/cm2, for example, is irradiated. If the tilt angle of the side wall of the tapered groove is 75° in this case, the effective irradiation energy density of the laser beam 64 irradiated onto the side wall dramatically drops to cos 75°×1.4 J/cm2=0.36 J/cm2, with which dopants implanted in the side wall are not sufficiently activated.
On the other hand, as shown in FIG. 32, in order to activate the dopants implanted in the side wall of the tapered groove, the irradiation energy density of the laser beam 65 must be increased to four times thereof, but in this case, the irradiation energy density of the laser beam 65, that is irradiated onto the plane, also becomes four times thereof, and abrasion and crystal defects may be generated, or [crystals] may change into an amorphous state.
In concrete terms, if the tilt angle of the side wall of the tapered groove is 75°, irradiation energy density of the laser beam 65 must be 1/cos 75°×1.4 J/cm2=5.4 J/cm2 in order to obtain the 1.4 J/cm2 effective energy density to be irradiated onto the side wall. With this however, a laser beam with excessive irradiation energy density is irradiated onto the plane, so abrasion and crystal defects may be generated on the plane, or [crystals] may change into an amorphous state.